Companding Law:
Factory Lead Time:
JESD-609 Code:
Max Supply Voltage:
Min Supply Voltage:
Nominal Supply Current:
Number of ADCs / DACs:
Number of Analog Inputs:
Number of Bits:
Number of Channels:
Number of Pins:
Number of Terminations:
Pbfree Code:
Peak Reflow Temperature (Cel):
Power Consumption:
Resolution (Bits):
Sigma Delta:
Signal to Noise Ratio (SNR):
Supply Voltage:
Terminal Pitch:
Terminal Position:
Termination:
Thickness:
Time@Peak Reflow Temperature-Max (s):
Voltage - Supply, Analog:
23 Records
RFQ
BOM